1. Field of the Invention
The present invention relates generally to semiconductor circuits and, more particularly, to a process for making self-aligning conductive vias used in interconnection structures.
2. Description of the Related Art
Interconnect structures of integrated circuits (ICs) generally take the form of patterned metallization lines that are used to electrically interconnect devices and to provide interconnection with external circuitry. By way of example, IC devices may include metal oxide semiconductor ("MOS") devices having diffused source and drain regions separated by channel regions, and gates located over the channel regions. In practice, an IC chip may include thousands or millions of devices, such as MOS transistors.
Conventionally, a dielectric layer (e.g., silicon oxide) is deposited over the devices, and via holes are patterned and formed through the dielectric layer to the devices below. As is well known in the art, photolithography "patterning" is typically accomplished by depositing a photoresist layer over the dielectric layer, selectively exposing the photoresist to light through a patterned reticle having via hole patterns, developing the photoresist to form a resist via mask, and etching the exposed dielectric layer to form via holes leading to a lower level. Once the via holes are formed, a conductive material is used to fill the via holes to define what are known as "metal contacts." Once the metal contacts are formed, a metallization layer is formed over the dielectric layer and the contacts. The metallization layer is then patterned using conventional photolithography techniques to define a first level of interconnect metal routing. This process may then be repeated if additional layers of metallization lines are desired.
One problem with conventional metal contact interconnect structures is misalignments introduced in the photolithography process. As mentioned above, via holes are typically defined through a dielectric layer with the purpose of forming an "electrical" metal contact between a layer underlying the dielectric layer and a layer overlying the dielectric layer. As circuits become increasingly smaller and dense, interconnect structures between successive patterned metal layers have also become ever more dense. Unfortunately, conventional photolithography techniques are also being pushed to their limit, which has had the effect of introducing misalignments between patterned layers.
FIG. 1A is a cross sectional view of a conventional semiconductor device having a misaligned metal contact 28. The semiconductor device includes a semiconductor substrate 10 having diffusion regions 12 and a polysilicon gate 14 defined between the diffusion regions. A first dielectric layer 19 is deposited over the semiconductor substrate 10, the diffusion regions 12 and the polysilicon gate 14. Next, via holes are defined through the first dielectric layer 19 down to the polysilicon gate 14 and the diffusion region 12 (i.e., source/drain). The via holes are then conductively filled with tungsten or metal to define conductive contacts 16 and 18. In this example, conductive contacts 16 and 18 are somewhat misaligned, but no significant electrical problem occurred in this case. However, serious misalignments are shown to have occurred in the patterning of a conductive contact 28, which is defined through a second dielectric layer 22.
As can be appreciated, these type of misalignments are becoming ever more prevalent as device feature sizes continue to shrink. As illustrated, the misalignment of conductive contact 28, which is used to interconnect a metal-1 line 24 to a metal-2 line 30, may cause electrical shorts between adjacently patterned features. By way of example, when interconnect density patterns increase, layout "design rules" that are used by designers to determine the closest possible inter-feature spacings are necessarily pushed to their limits. That is, although features are designed to be adequately spaced apart to avoid electrical shorts between features, misalignments (which are unavoidable in dense photolithography patterning) will cause features to be laid out in arrangements that seriously violate minimum inter-feature separations dictated the design rules.
FIG. 1B is a block diagram illustrating the inter-feature violations caused when misalignments in conductive contacts occur. For exemplary purposes only, assuming that a 0.18 micron technology processes is used to fabricate the semiconductor device of FIG. 1A, the minimum inter-feature spacing "Sw" will be about 0.3 microns, and the features widths "Fw" will be about 0.3 microns. However, due to the aforementioned misalignment problems described above, an error width "Ew" of about .+-.0.09 microns must be accounted for due to photolithography misalignments. As such, the spacing between metal-1 line 24 and metal-2 line 30 will be dangerously close (i.e., about 0.21 microns or less), thereby exposing the semiconductor device to future failures due to electrical shorts, leakage currents, or performance degradation caused by electrical coupling. In any event, these misalignments are commonly to blame for substantial losses in yield as well as below average device reliability.
FIGS. 1C and 1D illustrate another problem caused by a misalignments in a conductive contact 34 defined through a third dielectric layer 35 to electrically connect to metal-2 line 30. In this example, although electrical interconnection is not desired between metal-1 line 24, the misaligned via hole will necessarily cause the formation of the conductive contact 34 dangerously close to metal-1 line 24. As shown in FIG. 1D, the separation 40 between these electrically distinct features are also commonly to blame for yield reducing shorts, current leakage, and reliability problems. Further yet, as device features continue to shrink to even smaller process technologies, even smaller misalignments may cause yield reducing problems.
Accordingly, in view of the foregoing, there is a need for a process for fabricating interconnect conductive contacts that do not introduce the aforementioned yield reducing and reliability problems associated with misalignments between successive fabricated semiconductor layers.